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NX15 PCB Integration

This page provides a practical checklist for integrating the NX15 module into a custom host PCB.

It focuses on board-level integration. Detailed LGA pad usage is covered in NX15 LGA Pad Layout, and assembly handling is covered in NX15 Handling & Soldering.


PCB Integration Flow

StepAction
1Select the NX15 model
2Place the module on the host PCB
3Connect power and ground
4Add required decoupling capacitors
5Route SWD programming/debug pins
6Route reset and required GPIO
7Check antenna area or u.FL RF path
8Add test points for bring-up
9Review manufacturing and reflow requirements
10Validate the first prototype

Module Placement

Place the module so that power, debug, GPIO, and antenna constraints can be satisfied.

AreaRecommendation
PCB edgePreferred for chip antenna variants
Antenna areaKeep clear according to antenna layout rules
Debug accessKeep SWD pins accessible
Test pointsAdd test points for VDD, GND, reset, and debug
Mechanical areaAvoid placing metal or battery too close to antenna area

Power and Ground

Signal / AreaRecommendation
VDD_nRFUse a stable 1.7–3.6 V supply
GNDConnect every GND pad to a solid ground plane
DecouplingPlace 100 nF + 1 µF capacitors close to each VDD pad
Return pathKeep ground return path short and low impedance
Power test pointAdd a VDD test point for bring-up measurement
caution

Do not power the first prototype before checking VDD/GND continuity and confirming that no power rail is shorted.


Programming and Debug Access

NX40 Variant

Keep SWD access available during development and production.

SignalPurposeRecommendation
SWDIOProgramming/debug dataRoute to header or test pad
SWDCLKProgramming/debug clockRoute to header or test pad
NRESETReset controlRoute to button, header, or test pad
GNDDebug referenceInclude near SWD pins
VDD senseTarget voltage referenceAdd if required by debugger
tip

Even if the final product does not expose a debug connector, test pads are recommended for flashing, recovery, and production programming.


GPIO and Peripheral Routing

NX15 GPIO pins can be assigned to different peripheral functions through firmware configuration.

InterfaceRouting Note
UARTConfirm TX/RX direction and voltage level
SPIKeep clock and data routing clean, especially at higher speed
I2CAdd pull-up resistors as required by the bus design
PWMCheck output load and drive requirements
ADCKeep analog traces away from noisy or high-speed traces
PDMKeep clock/data routing short and clean
GPIOConfirm active level, pull-up/pull-down, and wake-up behavior
caution

Do not finalize GPIO routing before checking the firmware pin assignment and model variant constraints.


Antenna Integration Reminder

This page does not repeat full antenna rules, but antenna constraints must be checked before PCB release.

VariantRequired Check
NX15iChip antenna keep-out and PCB edge placement
NX15Eu.FL connector, 50 Ω RF trace, and solid GND reference

For full details, see the NX15 antenna design page in the NX15 Series BLE Module section.


Bring-up Test Points

Add test points for early validation.

Test PointPurpose
VDD_nRFVerify supply voltage
GNDMeasurement reference
SWDIOProgramming/debug
SWDCLKProgramming/debug
NRESETReset and recovery
UART TX/RXOptional log or host communication
Key GPIOApplication-specific validation

First Prototype Checklist

Before firmware testing:

CheckStatus
Correct NX15 model mounted
VDD_nRF voltage is correct
All GND pads are connected
Decoupling capacitors are placed correctly
SWDIO / SWDCLK are accessible
NRESET is accessible
Antenna layout is reviewed
No visible soldering defect
Current limit is set during first power-on