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NX15 Hardware Design

This page provides the basic hardware design guidelines for integrating the NX15 Series BLE module into a host board.

It focuses on power, ground, GPIO usage, programming/debug access, reset, and PCB-level bring-up requirements.

note

This page does not cover antenna layout in detail. For chip antenna keep-out and u.FL RF trace design, see NX15 Antenna Design.


Hardware Design Flow

Use this checklist before finalizing the host PCB.

StepDesign AreaGoal
1Power inputProvide a stable supply within the recommended range
2GroundConnect all GND pads to a solid ground plane
3DecouplingPlace bypass capacitors close to VDD pads
4Programming / debugRoute SWDIO, SWDCLK, GND, and reset to accessible pads
5ResetProvide a reliable NRESET path
6GPIO planningConfirm pin function before PCB finalization
7Interface routingRoute UART, SPI, I2C, PWM, ADC, or PDM as required
8Bring-up accessKeep test points available for early validation

Power Supply

NX15 uses VDD_nRF as the main supply input.

ItemRecommendation
Supply range1.7 V to 3.6 V
Typical supply3.3 V
Power railKeep stable during radio TX/RX activity
DecouplingPlace 100 nF + 1 µF capacitors close to each VDD pad
Ground returnUse a short, low-impedance return path to the ground plane
caution

Do not use the absolute maximum rating as the normal design target. Design the product using the recommended operating range.


Ground Design

All GND pads should be connected to a solid ground plane.

RuleWhy It Matters
Connect every GND padPrevents floating ground pads and unstable behavior
Use short vias to groundReduces impedance and improves RF / thermal return
Keep ground plane continuousHelps RF performance and power stability
Avoid splitting ground below the modulePrevents unpredictable return current paths
tip

For BLE modules, ground design affects both electrical stability and RF performance. Treat the GND pads as part of the RF reference path, not only as power return.


Programming and Debugging

NX15 provides SWDIO and SWDCLK for firmware programming and debugging.

SignalPurposeRecommendation
SWDIOSerial Wire Debug dataRoute to SWD header or test pad
SWDCLKSerial Wire Debug clockRoute to SWD header or test pad
GNDDebug referenceRoute to the same debug connector
NRESETReset controlRoute to debug connector or test pad

Keep these signals accessible during development and production.

note

Even if the final product does not expose a full debug connector, test pads are strongly recommended for firmware flashing, recovery, and production programming.


Reset Design

The NRESET pin is an active-low system reset signal.

ItemRecommendation
Reset accessRoute NRESET to a reset button or debug connector
Firmware recoveryKeep NRESET accessible during bring-up
Production testProvide test pad access if no button is used
Pull-up / reset circuitFollow the reference circuit recommendation

A reliable reset path is important for firmware flashing, debugging, and board-level recovery.


GPIO and Interface Planning

NX15 GPIO pins can be mapped to different peripheral functions through firmware configuration.

InterfaceTypical Use
UARTHost communication, logging, simple command/data interface
SPIExternal sensors, peripherals, or memory-related functions
I2CLow-speed sensors and configuration devices
PWMLED, buzzer, or control output
ADCAnalog sensor input
PDMDigital microphone input
GPIOButtons, interrupts, enable pins, status lines
caution

GPIO availability depends on firmware configuration and module variant. On Flash models, verify whether QSPI-related pins are reserved before using them as general-purpose GPIO.


Analog Input Notes

Some pins can be used as analog input channels.

Design ItemRecommendation
Analog tracesKeep away from noisy or high-speed signals
Input protectionAdd protection if the signal comes from outside the board
FilteringAdd RC filtering when required by the sensor
Voltage rangeKeep input voltage within allowed GPIO / ADC limits

Clock / NFC / Special Function Pins

Some pins may have special functions depending on the firmware configuration.

Pin GroupPossible FunctionDesign Note
XL1 / XL232.768 kHz LFXO or GPIOReserve if external low-frequency crystal is used
NFC1 / NFC2NFC antenna pins or GPIOKeep as NFC pins if NFC is required
SWODebug trace or GPIOUse as SWO only when debug trace is required
QSPI-related pinsExternal Flash function or GPIOCheck carefully on Flash models

Basic PCB Design Rules

Use the following rules as the minimum hardware design checklist.

RuleDescription
GNDConnect all GND pads to a solid ground plane
DecouplingPlace 100 nF + 1 µF capacitors near each VDD pin
RF areaMaintain antenna keep-out around the antenna edge
RF traceUse 50 Ω controlled impedance for RF feed traces
DebugKeep SWDIO, SWDCLK, GND, and NRESET accessible
Test pointsAdd test points for key power and debug signals

Hardware Bring-up Checklist

Before applying power to the first prototype, check:

ItemStatus
VDD_nRF is within the recommended operating range
All GND pads are connected to a solid ground plane
Decoupling capacitors are placed close to VDD pads
SWDIO and SWDCLK are accessible
NRESET is accessible
GPIO functions match firmware configuration
Antenna area follows the correct layout rules
Test points are available for debugging

What Not to Include Here

To avoid duplicate content, the following topics are handled in separate pages:

TopicGo To
Chip antenna keep-out and u.FL RF traceNX15 Antenna Design
Sleep current and firmware power tuningNX15 Low Power Guide
BLE advertising and GATT servicesNX15 BLE Application Guide
Model variant selectionNX15 Module Integration / Model Selection
LGA pad detailNX15 Module Integration / LGA Pad Layout